Distributed spintronic/CMOS sensor network for thermal aware systems

ABSTRACT

A hybrid integrated thermal sensor device includes a magnetic tunnel junction (MTJ) device electrically coupled in series with at least one CMOS transistor and disposed between a voltage rail terminal and a ground terminal. An output terminal is electrically coupled to a drain of the at least one CMOS transistor. The MTJ operates in an anti-parallel state and the output terminal provides a voltage indicative of a temperature of the MTJ device based on an MTJ antiparallel resistance. A distributed sensor network for real-time thermal mapping of an integrated circuit (IC) is also described.

STATEMENT REGARDING FEDERALLY FUNDED RESEARCH OR DEVELOPMENT

This invention was made with government support under CCF-1716091awarded by the National Science Foundation. The government has certainrights in the invention.

FIELD OF THE APPLICATION

The application relates to thermal measurements within an integratedcircuit (IC), particularly to sensor network to generate a thermal mapof an internal structure of an IC.

BACKGROUND

Recent developments in IC technology rely on device scaling and 3-Dintegration, resulting in billions of devices compacted into a smallarea. These techniques deteriorate the system lifetime and reliabilitydue to an increase in system temperature due to high power densities.

SUMMARY

A hybrid integrated thermal sensor device includes a magnetic tunneljunction (MTJ) device electrically coupled in series with at least oneCMOS transistor and disposed between a voltage rail terminal and aground terminal. An output terminal is electrically coupled to a drainof the at least one CMOS transistor. The MTJ operates in ananti-parallel state and the output terminal provides a voltageindicative of a temperature of the MTJ device based on an MTJantiparallel resistance.

The MTJ can be disposed between a ground terminal and a source terminalof the at least one CMOS transistor, and a second CMOS transistor isdisposed between a drain terminal of the at least one CMOS transistorand voltage rail.

The at least one CMOS transistor can be configured as a common sourceamplifier.

The second CMOS transistor can be configured as an active load.

The active load can include a PMOS based current source.

The hybrid integrated thermal sensor device can further include anenable terminal electrically coupled to a gate of at least one CMOStransistor.

The output terminal can be electrically coupled to a first inputterminal of a comparator, and a second input of the comparatorelectrically coupled to a settable reference voltage.

The hybrid integrated thermal sensor device can operate as a one bitdigital thermal sensor with a settable threshold temperature.

The comparator can further include a sensor amplifier enable (SAEN)terminal electrically coupled to the comparator.

A distributed sensor network for real-time thermal mapping of anintegrated circuit (IC) includes a control unit disposed in the IC. Aplurality of hybrid MTJ/CMOS integrated thermal sensor devices areelectrically coupled to the control unit. The control unit reads of eachthe hybrid MTJ/CMOS integrated thermal sensor devices to generatesubstantially in real-time, a thermal map of the IC.

The plurality of hybrid MTJ/CMOS integrated thermal sensor devices caninclude more than about 100 devices.

The plurality of hybrid MTJ/CMOS integrated thermal sensor devices caninclude one bit digital thermal sensors with a plurality of same ordifferent settable threshold temperatures.

The distributed sensor network can further include a multiplexer circuitto switch a reference between different voltages to vary the settablethreshold temperature of the one bit digital thermal sensors.

The plurality of hybrid MTJ/CMOS integrated thermal sensor devices canbe configured in a grid based topology of m×n sensor nodes of m columnsand n row.

The thermal map can include nodes below or above a threshold setting ofeach of the hybrid MTJ/CMOS integrated thermal sensor devices.

Each of the plurality of hybrid MTJ/CMOS integrated thermal sensordevices can be sequentially enabled and read by the control unit.

The control unit or a different control unit of the IC can dynamicallymanage at least one system of the IC based on the thermal map tomitigate deterioration of a lifetime of the IC or a reliability of theIC.

The control unit, or a different control unit, dynamically can configuresubstantially in real-time at least one logic module or at least onememory module of the IC based on the thermal map of the IC.

Based on the thermal map, the control unit, or the different controlunit dynamically can move execution of a logic or an execution of amemory function from one module to a different similar function moduleof the IC dynamically in time to balance a thermal load between modulesor to prevent an overheating of a module.

Based on the thermal map, the control unit, or the different controlunit, can dynamically reconfigures the IC to optimize a thermalcondition of the IC.

The foregoing and other aspects, features, and advantages of theapplication will become more apparent from the following description andfrom the claims.

BRIEF DESCRIPTION OF THE DRAWINGS

The features of the application can be better understood with referenceto the drawings described below, and the claims. The drawings are notnecessarily to scale, emphasis instead generally being placed uponillustrating the principles described herein. In the drawings, likenumerals are used to indicate like parts throughout the various views.

FIG. 1 is a drawing showing an exemplary distributed thermal networksystem according to the Application;

FIG. 2 is a drawing showing an exemplary distributed thermal networksystem according to the Application in more detail;

FIG. 3 is a schematic diagram showing an exemplary on-chip analogthermal sensor according to the Application;

FIG. 4 is a waveform diagram showing an exemplary data signal waveformof a 4×4 data signal;

FIG. 5A is a grid showing exemplary output sensor node readings;

FIG. 5B is a grid showing a thermal map for the output sensor nodereadings of FIG. 5A;

FIG. 6 is a drawing showing an exemplary MTJ, interconnects, and devicelayers structure;

FIG. 7 is a graph showing a normalized sensing current of an exemplaryAP MTJ at different sense voltages;

FIG. 8 is a schematic diagram showing an exemplary MTJ/CMOS-basedthermal sensor according to the Application;

FIG. 9A is a schematic diagram showing a diode connected transistortemperature sensor;

FIG. 9B is a schematic diagram showing a paired two transistortemperature sensor;

FIG. 9C is a schematic diagram showing an exemplary hybridMTJ/transistor temperature sensor according to the Application;

FIG. 9D is a schematic diagram showing an exemplary hybridMTJ/transistor with an active load temperature sensor according to theApplication;

FIG. 10 is a table (Table I) showing a comparison of the new temperaturesensor devices of the Application (FIG. 9C and FIG. 9D), andconventional CMOS sensors (FIG. 9A and FIG. 9B in terms of sensitivity,linearity, power consumption, and area;

FIG. 11 is a schematic diagram showing a sensor signal path;

FIG. 12 is a table (Table II) showing characteristics of exemplarydistributed thermal networks of different grid sizes;

FIG. 13A is a graph showing the temperature at a system node versustime;

FIG. 13B is a graph showing the system node output for V_(ref)=300 mVwhich maps to a threshold temperature of T=332 K;

FIG. 13C is a graph showing the system node output for V_(ref)=304 mVand T=343 K;

FIG. 13D is a graph showing the system node output for V_(ref)=306 mVand T=350 K;

FIG. 14 is a table (Table III) showing a comparison between the CMOS/MTJthermal sensor of the Application and that of reference [12];

FIG. 15 is a table (Table IV) showing MTJ physical parameters; and

FIG. 16 is a drawing showing an exemplary MJT structure suitable for usein a hybrid integrated thermal sensor device.

DETAILED DESCRIPTION

In the description, other than the bolded paragraph numbers, non-boldedsquare brackets (“[ ]”) refer to the citations listed hereinbelow.

As described hereinabove, Recent developments in IC technology rely ondevice scaling and 3-D integration, resulting in billions of devicescompacted into a small area. These techniques deteriorate the systemlifetime and reliability due to an increase in system temperature due tohigh power densities.

Dynamically managing a system based on the thermal characteristics isimportant to mitigate these issues of deterioration of system lifetimeand reliability. An on-chip thermal aware system which can includehundreds of distributed thermal sensors is described hereinbelow in thisApplication.

A new hybrid spintronic/CMOS based thermal sensor is also described thatexploits the thermal response and small area of an antiparallel magnetictunnel junction. The sensor cell can consume as little as 500 pJ to read1,024 thermal sensor nodes and can, for example, generate a thermal mapof a system composed of 32×32 thermal sensors. A sensor cell accordingto the Application, can exhibit a thermal linearity (R²) up to 0.983 anda thermal sensitivity of 1.91 mV/K over the commercial temperature rangeof 0° C. to 85° C. while consuming 32 μW.

The description which follows is in 7 Parts. The new thermal awaresystem is described in Part 2, where the system architecture and circuitrequirements are discussed. The new MTJ as a thermal sensor device isdiscussed in Part 3. A comparison between a CMOS diode and transistorbased thermal sensor with an MTJ/transistor temperature sensor isprovided in Part 3. Simulation results are presented in Part 4. Part 5briefly describes suitable MTJ elements. Part 6 is a summary, andAppendix I, MTJ macrospin model follows the summary.

Part 1 Introduction

Two primary methods are used to achieve next generation integratedsystems, a large number of deeply scaled devices and die stacking. Highpower densities and thermal issues such as long heat conduction pathsare produced, which, in turn, can dramatically degrade performance,reliability, leakage current, and system robustness [1, 2]. To managethe system workload and protect the system from overheating, methodssuch as allocating heat conduction paths and specialized cooling systemsare used [3, 4]. These systems should be supported with a temperatureaware capability to allocate and properly respond to critical hot spots.

A thermal aware system can be achieved by distributing a large number ofon-chip thermal sensors. These on-chip thermal sensors should be smallin size, low power, high speed, sensitive, and accurate over a widetemperature range. The on-chip thermal sensors should be appropriatelyplaced to accurately capture local hot spots. The location of thethermal sensors depends upon the sensor characteristics, systemrequirements, integrated circuit (IC) package, and cooling techniques[5].

A small number of thermal sensor nodes have typically been locatedaround an IC, particularly near potential hot spots to support a thermalaware system. For instance, Intel utilizes one thermal sensor per corein the Xeon 5400 series [6], while 25 thermal sensors are embeddedwithin the IBM POWER6 processor [7]. The use of a few thermal sensors,however, limits the ability to fully monitor the significant spatial anddynamic temperature variations across an integrated system [8].

Thermal aware systems manage the located distributed thermal sensornodes around an IC, dynamically controlling the system workload [8, 9,10]. These systems, however, utilize a software based management systemwhich does not respond to individual thermal sensor nodes. In addition,the response time of these software solutions is long and consumessignificant power; hence hardware solutions are desirable.

In this Application, an integrated system to support a thermal awarecapability, shown in FIG. 1, is described, where multiple thermal sensornodes are distributed across an IC.

The distributed thermal sensor nodes communicate with a centralizedsensing unit which collects temperature information from the individualsensor nodes, producing a thermal map of the system. A new type ofhybrid spintronic/CMOS based analog thermal sensor is also describedhereinbelow, where the high temperature sensitivity of the magnetictunnel junction (MTJ) antiparallel resistance is exploited. The sensoroutput is compared with a reference source, as shown in FIG. 3 [4]. Theanalog thermal sensor behaves as a threshold temperature-based sensor,triggering a signal if the temperature (or voltage) exceeds a certainreference temperature (or voltage).

Thermal sensors using spintronic technology have been previouslydescribed [11, 12]. For example, in [11], the influence of temperatureon the probability of device switching is noted. Sensing a change in theswitching probability requires additional circuitry.

However, as described by the Application in more detail hereinbelow, werealized that the temperature can be measured by a change in theantiparallel resistance.

The new system described by the Application includes a network ofthermal sensor nodes distributed around an IC and additional circuitry,described in more detail in part 2, that manages and controls the sensorsignals and hence the system performance, as schematically shown in FIG.1.

Part 2 Distributed Thermal Network

The thermal aware system of the Application includes a network ofthermal sensor nodes communicating with a control unit that collectstemperature data and produces a thermal map. This thermal networkprovides the monitored system with dynamic real-time thermalinformation. The system architecture, read and data signaling, andrelated circuitry are discussed below. The system components aredescribed in part 2A, the system signaling is illustrated in part 2B,and the ability to fabricate the system is described in part 2C.

Part 2A, System architecture—The system architecture, shown in FIG. 2,is managed as a memory grid, where the sensor nodes are organized in agrid-based topology. To read a system of m×n sensor nodes with m columnsand n rows, log₂ n-to-n decoder and m amplifiers are required. The inputto the system decoder identifies the row being read. Each row shares thesame enable signal, while each column shares the same bit line. Theenable signal, generated from a system decoder, writes the sensor nodevoltage to the bit line and is read through a sense amplifier. Thisexemplary sense amplifier is latch-based, composed of two inverterscontrolled by a Read signal. The sensor node voltage is compared with areference voltage that sets a threshold temperature. The system outputis in a binary format indicating whether the state of the sensor node iseither below or above a threshold voltage.

Part 2B, System read and data signaling—The sequence of operations is asfollows. During each read cycle, the enable signal controls the decoderto individually select one row. The output of each cycle is a vector ofm sensor node reads. During each cycle, one row is read, and n cyclesare required to read n rows. The system input is generated from acounter and the system output is stored within a memory.

An example of the data signal waveform of a 4×4 data signal is shown inFIG. 4. The decoder and sensor nodes are enabled by the Enable signal,where the decoder input data are annotated as A0, A1. The output of thedecoder enables the individual transmission gates. Each transmissiongate connects the associated sensor node output to the bit line. TheRead signal enables the sense amplifier to latch a bit line. Incomparison with a reference voltage, the amplifier output is latched toeither high or low. The output signals w0, w1, w2, and w3, indicate thetemperature status. By turning the Enable signal off, the system savesenergy by isolating the power from the sensor nodes and decoder.

FIG. 5A and FIG. 5B show a 16 by 16 thermal map. FIG. 5A is a gridshowing exemplary output sensor node readings. FIG. 5B is a grid showinga thermal map for the output sensor node readings of FIG. 5A. The darkareas represent nodes with a temperature above the temperaturethreshold. The output of the exemplary distributed thermal network iscomposed of 16×16 sensor nodes as illustrated in FIG. 5B. The binarythermal map, shown in FIG. 5A, reflects the location of the individualsensor nodes. The thermal map indicates if the temperature is above orbelow a predefined threshold temperature and hence determines inreal-time the location of the critical hot spots.

Part 2C, System Implementation—The new system of the Applicationincorporates hybrid spintronic/CMOS devices. The spintronic circuit isbased on a magnetic tunnel junction. An MTJ is a structure composed oftwo ferromagnetic layers separated by an insulator barrier [13]. Theresistance of the device is controlled by the difference in themagnetization angle between the two layers. The device exhibits twostable states, a parallel (P) state (where the two layers are magnetizedin the same direction) and an antiparallel (AP) state [14]. The MTJ iscombined with CMOS to provide an efficient temperature sensing element.An MTJ/CMOS based thermal sensor exhibits small size, low power, highlinearity, and high sensitivity [15]. These capabilities support usewithin a thermal aware system with hundreds of distributed thermalsensor nodes.

The MTJ is integrated between the metallic layers above the CMOS devicelayers, as shown in FIG. 6, making this structure a good candidate for alocal, distributed thermal sensor. MTJ fabrication is sufficientlymature for different technology platforms such as bulk-CMOS, FDSOI-CMOS,and FINFET CMOS [16]. Intel [17], GlobalFoundries [18], Samsung [19],and other large foundries are integrating MTJ technology with CMOS atdifferent technology nodes. These advancements in fabrication canproduce high quality MTJs for thermal sensing applications. In addition,MTJ memory can operate over a wide range of temperatures, −40° C. to125° C., in a stable manner for commercial, automotive, and militaryapplications [20]. The ability of MTJ technology to be integrated withCMOS, operate over a wide, stable temperature range, and exhibit almostzero leakage current in the off state, with higher temperaturesensitivity than conventional CMOS devices suggests an MTJ/CMOStemperature sensor is an effective candidate for next generation thermalaware systems [15].

MTJ as a thermal sensor is supported by the high thermal sensitivity ofthe MTJ antiparallel resistance. The resistance of an MTJ changes almostlinearly with high sensitivity with temperature in the antiparallelstate (as compared to the parallel state) [21], [22], [23], [24]. Thesensitivity of an MTJ to temperature has been described in multiple MTJstructures such as, CoFeB/Al-O/CoFeB [21], [22], Fe/MgO/Fe [23], andCoFeB/MgO/CoFeB [24]. The MTJ resistivity changes almost linearly withtemperature in the antiparallel state (as compared to the parallelstate) [19]. The thermal sensitivity of the MTJ antiparallel resistancedepends upon the device material structure, dimensions, and appliedsense voltage.

The temperature sensor cell is discussed in the following section. Thephysical, magnetic, and electrical behavior of an MTJ in addition to thedescribed thermal sensor circuit are reviewed. A comparison between thenew temperature sensors of the Application and conventional CMOS sensorsin terms of sensitivity, linearity, power consumption, and area is alsoprovided.

Part 3 Integrated Solutions for Thermal Monitoring

A variety of CMOS-based integrated electronic devices and circuits canproduce a thermal response [25]. The most commonly used temperaturesensor is the Brokaw bandgap circuit where a voltage or current producesa proportional-to-absolute temperature (PTAT) relationship [26, 27].This circuit requires at least two large bipolar transistors to extractthe PTAT signal. Other thermal sensors are based on a change in thethreshold voltage of the diode or transistor with temperature [28]. Thischange in threshold voltage with temperature is exponential, requiringadditional circuitry such as a threshold voltage extractor circuit [28]or look-up table [29] to accurately predict the temperature. Drawbacksof these technologies are high leakage current, large device capacitance(which influences the circuit response), poor stability, and lowsensitivity over a wide temperature range with thermal cycling [4]. Theneed for calibration prior to use and low sensitivity with devicescaling are also common issues [4].

This application describes a spintronic device, the MTJ, in a new use asa thermal sensing element for large scale distributed systems.

Temperature influences the MTJ device magnetic anisotropy, antiparallelresistance, charge magnetic polarization, and thermal induced magneticfield [30]. The influence of both the sense voltage and temperature onan MTJ is discussed in Part 3A. A comparison between four thermalsensors (a diode connected transistor, two paired transistors, a hybridMTJ/transistor, and a hybrid MTJ/transistor with an active load) isdescribed in Part 3B.

Part 3A, MTJ as an integrated thermal sensor—A macrospin model,described in the Appendix, is used here. The model includes theinfluence of the sense voltage and temperature on the device tunnelingmagnetoresistance TMR (T, V), layer spin polarization P(T), saturationmagnetization M_(S) (T), device magnetic anisotropy constant K(T), andvoltage controlled magnetic ansitropy (VCMA) constant ζ_(VCMA)(T).

The influence of temperature on the conductance of an MTJ is the sum oftwo components, as described by (0); a spin dependent (elastic) term dueto the thermal excitation of the spin polarized electrons, and a spinindependent term (inelastic) due to scattering by defects/impuritystates. The device antiparallel resistance decreases with an increase intemperature. Under different sense voltages, the device exhibits adifferent sensitivity rate, as shown in FIG. 7. FIG. 7 is a graphshowing a normalized sensing current of an exemplary AP MTJ at differentsense voltages [30].

The sensing technique considers the effects of temperature and sensevoltage on the thermal stability and resistance of an MTJ. Hence, an MTJoperates in the stable AP state despite fluctuations in operatingtemperature and supply voltage. The thermal stability Δ of an MTJdetermines the limits of the applied voltage and range of temperatureover which the device can stably operate without switching [30]. Δ isthe ratio of the magnetization energy of an MTJ and the thermalperturbation to the system, which is a function of temperature andapplied voltage,

$\begin{matrix}{{{\Delta( {T,V} )} = {\frac{{\Delta{E( {T,V} )}}❘_{MTJ}}{K_{B}T} = \frac{{K_{eff}( {T,V} )}v_{FM}}{K_{B}T}}},} & {(1),}\end{matrix}$where K_(B) is the Boltzmann constant, ΔE (T, V)|_(MTJ) is the systemanisotropy energy of an MTJ, K_(eff) is the effective anisotropyconstant, and v_(FM) is the volume of the FM layer.

An exemplary MTJ-based thermal sensor according to the Application isillustrated in FIG. 8, where a common source amplifier with a PMOS basedcurrent source behaves as an active load. The active load bias anddevice size determines the circuit sensitivity. The increase in circuitsensitivity and linearity with temperature is compared in 3B with CMOSonly based thermal sensors.

Part 3B, Comparison with conventional integrated solutions—A new hybridMTJ/CMOS based thermal sensor is described in this Application. Thecircuit benefits from the influence of temperature on both thetransistor threshold voltage and the MTJ antiparallel resistance. Acomparison between four different circuits clarifies the advantages ofan MTJ with CMOS as a thermal sensor. The four circuits are shown inFIG. 9A to FIG. 9D.

FIG. 9A and FIG. 9B show circuits which are CMOS only thermal sensors,where the circuit of FIG. 9A is a diode connected transistor basedthermal sensor biased by a current source, and circuit of FIG. 9B is thesame as circuit of FIG. 9A followed by a common source amplifier stage.In the circuit of FIG. 9B, the two transistors perform temperaturesensing, which enhances the circuit stability and linearity withtemperature.

The circuits FIG. 9C and FIG. 9D are MTJ/CMOS based thermal sensorsaccording to the Application. A comparison of these sensor circuits islisted in Table I of FIG. 10. FIG. 10, Table I shows a comparison of thenew temperature sensor devices of the Application (FIG. 9C and FIG. 9D),and conventional CMOS sensors (FIG. 9A and FIG. 9B in terms ofsensitivity, linearity, power consumption, and area. The simulationresults are based on the MTJ macrospin compact model [30] of a VCMA PMTJand the predictive transistor model (16 nm PTM) for CMOS transistors[31]. The CMOS transistors are sized the same (32 nm×16 nm) and biasedat the same current (31 nA) to establish a fair comparison.

For the two CMOS thermal sensors, the circuits exhibit good sensitivitywith reasonable linearity. In the circuit of FIG. 9D, the two CMOStransistors and MTJ behave as temperature sensing elements. The circuitof FIG. 9D exhibits higher thermal sensitivity than of FIG. 9C. In termsof power consumption, the circuit of FIG. 9D exhibits the lowest powerconsumption. The MTJ/CMOS based thermal sensor requires less areabecause no current source is required. The circuit of FIG. 9B exhibitshigher linearity than the circuit of FIG. 9A, however, the circuit ofFIG. 9B requires larger transistors than the circuit of FIG. 9A.

Based on Comparison, the circuit of FIG. 9D is preferred (over thecircuit of FIG. 9C) for use as the system-wide temperature sensor in thethermal aware system of the Application. In the following section,simulation results of the system of the Application incorporating thehybrid MTJ/transistor thermal sensor node are presented. A comparisonbetween the thermal aware system of the Application in terms of energyconsumption, delay, and system size is also described.

CMOS structures of the hybrid integrated thermal sensor device aretypically fabricated on device layer (e.g. FIG. 6, device layer). Anysuitable CMOS fabrication techniques and structures can be used,including, for example, bulk-CMOS, FDSOI-CMOS, and FINFET CMOS.

Part 4 Simulation Results

An exemplary system operation works as follows. The sense amplifier setsthe sensor node voltage. Based on the grid size and number of nodes,preamplifier stages or buffers can be used to increase the current,enhance the sensitivity, and isolate the sensor node signal.

FIG. 11 is a schematic diagram showing a sensor signal path. The signalpath of the sensor node to the output, shown in FIG. 11, is used tocharacterize system performance.

FIG. 12, Table II shows characteristics of exemplary distributed thermalnetworks of different grid sizes. The power consumption includes theenergy consumed in the sensor nodes, buffers, inverters, amplifiers, anddecoder. The delay of the read operation is the time required to readeach of the rows.

A read pulse of 1 ns is used to produce an output decision of one sensornode. The comparator delay is 0.03 ns. The accuracy of the exemplarysystem temperature is ±3K for a reference voltage with an accuracy of ±1mV. The area of each sensor node is 32 nm×64 nm where the MTJ layer isbetween the second and third interconnect layer, as shown in FIG. 6.Because of the influence of manufacturing process variations, the sensornodes should be calibrated prior to use. Different calibration schemesof multiple on-chip thermal sensors have been proposed [4]. The design,management, and control of these thermal sensors are the foci of thispaper.

FIG. 13A to FIG. 13D are graphs showing a system node output fordifferent temperature threshold settings. FIG. 13A is a graph showingthe temperature at a system node versus time. FIG. 13B is a graphshowing the system node output for V_(ref)=300 mV which maps to athreshold temperature of T=332 K. FIG. 13C is a graph showing the systemnode output for V_(ref)=304 mV and T=343 K. FIG. 13D is a graph showingthe system node output for V_(ref)=306 mV and T=350 K. An example of thesystem node output at three different reference voltages, 300 mV, 304mV, and 306 mV, mapped to, respectively, threshold temperatures of 332K, 343 K, and 350 K is shown in FIG. 13A to FIG. 13D. A multiplexercircuit can be added to switch the reference signal between differentvoltages to vary the threshold temperature of the sensor nodes.

A comparison between the proposed hybrid CMOS/MTJ thermal sensor and[12] in terms of system requirements, sensing scheme, energy, readaccuracy, and temperature range is listed in FIG. 14, Table III. TheApplication describes a hybrid MTJ/CMOS-based thermal sensor and arelated thermal aware system. The Application also describes adistributed thermal sensor network able to provide an updated spacialand temporal thermal map in real-time.

The system described by the Application provides flexibility in choosinga threshold temperature. The system can also support a multi-thresholdsensing scheme. This capability can be achieved by multiplexing thereference voltage. At each reference voltage, the system identifieswhether the temperature at a sensor node is above or below a certainthreshold temperature. As an example, with two different referencevoltages, the system could identify the temperature at a sensor nodewithin three different temperature regions (below T1, between T1 and T2,or above T2).

With hundreds of on-chip thermal sensor nodes distributed across asystem, the ability to monitor local heat (characterizing the generatedheat and thermal paths) is achieved. This kind of real-time spacial andtemporal sensing capability provides significant informationcharacterizing the thermal behavior which can be used to mitigate heatgeneration and distribution issues.

Part 5 MTJ

Any suitable MTJ can be used where the MTJ can be operated as atemperature sensor, preferably in an anti-parallel state so that atemperature measurement over the operating temperature range of the MTJdevice is based on an MTJ antiparallel resistance.

FIG. 16 is a drawing showing one exemplary MJT structure which issuitable for use in a hybrid integrated thermal sensor device asdescribed hereinabove (e.g. FIG. 8, FIG. 9c , and FIG. 9d ). The MJT ofFIG. 16 includes ferromagnetic layers 1501 separated by an insulationlayer 1503. The MTJ structure of FIG. 16 can be built or fabricatedabove a heavy metal layer.

Other suitable MJTs include a heavy metal layer, such as, for example,the MJT base element described by U.S. Pat. No. 10,510,474 B2, SWITCHINGOF PERPENDICULARLY MAGNETIZED NANOMAGNETS WITH SPIN-ORBIT TORQUES IN THEABSENCE OF EXTERNAL MAGNETIC FIELDS, and co-pending CIP application U.S.patent application Ser. No. 16/850,173, SWITCHING OF PERPENDICULARLYMAGNETIZED NANOMAGNETS WITH SPIN-ORBIT TORQUES IN THE ABSENCE OFEXTERNAL MAGNETIC FIELDS, also assigned to the University of Rochester.Both of the '474 patent and '173 application describe exemplary suitablematerials and fabrication techniques for MJTs. The '474 patent and '173application are both incorporated herein by reference in their entiretyfor all purposes.

Generally, a magnetic tunnel junction includes at least two nanomagnets(magnetic free layers) separated by a tunnel barrier. Those skilled inthe art of integrated MJT devices will understand that suitable MJTs foruse in the new device, system, and methods according the Application,may include additional layers, such as, for example, non-magneticlayers, antiferromagnetic layers, electrode layer, etc., andcombinations thereof. Any suitable MJT structure wherein the MTJoperates in an anti-parallel state can be used.

Part 6 Summary

The need for a thermal aware system increases with device scaling andthe size of the integrated system. A thermal aware system is describedwhere a grid structure is composed of individual thermal sensor cells.The sensor nodes are based on hybrid spintronic/CMOS technology, wherethe antiparallel resistance of a magnetic tunnel junction exhibits athermal linearity of 0.9 and thermal sensitivity of 4.8 mv/K over atemperature range of −55° C. to 125° C. An exemplary system of 1,045thermal sensors distributed in a 32×32 grid structure consumesapproximately 500 pJ. A thousand of thermal sensor nodes according tothe Application can consume less than 1 nJ. Such low energy and highsensitivity sensor nodes are particularly appropriate for nextgeneration thermal aware systems.

The plurality of hybrid MTJ/CMOS integrated thermal sensor devices caninclude one bit digital thermal sensors with a settable thresholdtemperature. The system can be updated to include multiple thresholdtemperatures. A multiplexer can be added so the user can define multiplethreshold references which reflect multiple threshold temperatures.

A distributed sensor network as a thermal aware system as describedhereinabove, can use a control unit, or another on-chip controller todynamically configure at least one logic module or at least one memorymodule of an IC substantially in real-time based on said thermal map ofthe IC. The distributed sensor network can dynamically move execution ofa logic or execution of a memory function from one module to a differentsimilar function module of said IC dynamically in time to balance athermal load between modules or to prevent an overheating of a modulebased on the thermal map. The control unit, or another on-chipcontroller can dynamically reconfigure the IC to optimize substantiallyin real-time a thermal condition of said IC based on the thermal map.

APPENDIX I—MTJ MACROSPIN MODEL

A macrospin compact model which characterizes a voltage controlledmagnetic anisotropy (VCMA) MgO|CoFeB perpendicular MTJ is described here[30]. The model characterizes the dynamic response of the devicemagnetic and electrical performance. The magnetization dynamics of thedevice free ferromagnetic (FM) layer are described by the modifiedLandau-Lifshitz-Gilbert equation. The expression describes the dynamicmagnetic behavior of the FM layer as

$\begin{matrix}{{\frac{\partial\overset{arrow}{M}}{\partial t} = {{- {\frac{\gamma\mu_{o}}{1 + \alpha^{2}}\lbrack {{\overset{arrow}{M} \times {\overset{arrow}{H}}_{eff}} + {\alpha\overset{arrow}{M} \times \frac{\partial\overset{arrow}{M}}{\partial t}}} \rbrack}} + {\gamma{\sum{\overset{arrow}{\tau}}_{i}}}}},} & ( {A{.1}} )\end{matrix}$where {right arrow over (M)} is the normalized free layer magnetization,t is the time variable, {right arrow over (H)}_(eff) is the effectivemagnetic field expressed in A/m, y is the electron gyromagnetic ratio,y≈−2π×27.99 GHz/T, μ_(o) is the permeability of free space, a is theGilbert damping factor, and {right arrow over (τ)}_(i) is the torqueapplied due to other perturbations such as current which exerts a spintransfer torque [27]. The macrospin model is developed in associationwith the static and dynamic micromagnetic analysis of the system energy.The effective magnetic field applied to the free layer {right arrow over(H)}_(eff) is{right arrow over (H)} _(eff) ={right arrow over (H)} _(UA) −{rightarrow over (H)} _(dem) +{right arrow over (H)} _(c) +{right arrow over(H)} _(ext) −{right arrow over (H)} _(VCMA) +{right arrow over (H)}_(th),  (A-2)where {right arrow over (H)}_(UA) is the uniaxial anisotropy fieldsometimes defined as {right arrow over (H)}_(K), {right arrow over(H)}_(dem) is the demagnetization field, {right arrow over (H)}_(c) isthe coupling field due to the other FM layer, {right arrow over(H)}_(ext) is the applied external magnetic field, {right arrow over(H)}_(VCMA) is due to VCMA, and {right arrow over (H)}_(th) is thestochastic magnetic field due to thermal variations.

The MTJ antiparallel conductance is modeled as [28]G _(AP)(T)=G _(T)[1−P ₁(T)P ₂(T)]+G _(SI),  (A.3)

where G_(T)=G₀ (sin(CT)/CT) is the thermal smearing factor,G₀=(3.16×10¹⁰ √{square root over (ϕ_(B))}/t_(ox))exp(−1.025×√{squareroot over (ϕ_(B))}×t_(ox)) is the parallel state conductance at zerovoltage and zero temperature, T is the ambient temperature, ϕ_(B) is theaverage tunneling barrier height (in eV), t_(ox) is the thickness of theinsulator barrier layer, and C=1.387×10⁻⁴t_(ox)/√{square root over(ϕ_(B))} is a material dependent parameter [28]. G_(SI)=ST^(4/3) is theinelastic spin independent conductance, and S is a fitting parameter.The dependence of the spin polarization on temperature can be fitted as[29, 30]. P₁ and P₂ are the spin polarization percentage of the two FMlayers. The dependence of the spin polarization on temperature can befitted as [34, 21]P(T)=P(0)[1−β_(P) T ^(αP)],  (A.4)where β_(P) and α_(P) are fitting parameters related to the devicedimensions and material properties.

The physical parameters are based on perpendicular magnetic anisotropyand VCMA MgO|CoFeB [25,31,32]. The experimentally extracted modelparameters are listed in FIG. 15, Table IV, MTJ physical parameters.

Models, software, and firmware in support of a distributedspintronic/CMOS sensor network for thermal aware systems can be providedon a computer readable non-transitory storage medium. A computerreadable non-transitory storage medium as non-transitory data storageincludes any data stored on any suitable media in a non-fleeting mannerSuch data storage includes any suitable computer readable non-transitorystorage medium, including, but not limited to hard drives, non-volatileRAM, SSD devices, CDs, DVDs, etc.

It will be appreciated that variants of the above-disclosed and otherfeatures and functions, or alternatives thereof, may be combined intomany other different systems or applications. Various presentlyunforeseen or unanticipated alternatives, modifications, variations, orimprovements therein may be subsequently made by those skilled in theart which are also intended to be encompassed by the following claims.

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What is claimed is:
 1. A distributed sensor network for real-timethermal mapping of an integrated circuit (IC) comprising: a control unitdisposed in said IC; and a plurality of hybrid MTJ/CMOS integratedthermal sensor devices electrically coupled to said control unit;wherein said control unit reads each of said hybrid MTJ/CMOS integratedthermal sensor devices to generate substantially in real-time, a thermalmap of said IC, and wherein said plurality of hybrid MTJ/CMOS integratedthermal sensor devices comprises one bit digital thermal sensors with aplurality of same or different settable threshold temperatures.
 2. Thedistributed sensor network of claim 1, wherein said plurality of hybridMTJ/CMOS integrated thermal sensor devices comprises more than about 100devices.
 3. The distributed sensor network of claim 1, furthercomprising a multiplexer circuit to switch a reference voltage betweendifferent voltages to vary said settable threshold temperature of saidone bit digital thermal sensors.
 4. The distributed sensor network ofclaim 1, wherein said plurality of hybrid MTJ/CMOS integrated thermalsensor devices are configured in a grid based topology of m×n sensornodes of m columns and n rows.
 5. The distributed sensor network ofclaim 1, wherein said thermal map comprises nodes below or above athreshold setting of each of said hybrid MTJ/CMOS integrated thermalsensor devices.
 6. The distributed sensor network of claim 1, whereineach of said plurality of hybrid MTJ/CMOS integrated thermal sensordevices is sequentially enabled and read by said control unit.
 7. Thedistributed sensor network of claim 1, wherein said control unit or adifferent control unit of said IC dynamically manages at least onesystem of said IC based on said thermal map to mitigate deterioration ofa lifetime of said IC or a reliability of said IC.
 8. The distributedsensor network of claim 1, wherein said control unit, or a differentcontrol unit, dynamically configures substantially in real-time at leastone logic module or at least one memory module of said IC based on saidthermal map of said IC.
 9. The distributed sensor network of claim 8,wherein based on said thermal map, said control unit or said differentcontrol unit dynamically moves execution of a logic or an execution of amemory function from at least one module to a different similar functionmodule of said IC dynamically in time to balance a thermal load betweenmodules or to prevent an overheating of a module.
 10. The distributedsensor network of claim 8, wherein based on said thermal map, saidcontrol unit, or said different control unit, dynamically reconfiguressaid IC to optimize a thermal condition of said IC.